DocumentCode
2100450
Title
A fast sequential learning technique for real circuits with application to enhancing ATPG performance
Author
El-Maleh, Aiman ; Kassab, Mark ; Rajski, Janusz
Author_Institution
Mentor Graphics Corp., Beaverton, OR, USA
fYear
1998
fDate
19-19 June 1998
Firstpage
625
Lastpage
631
Abstract
This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.
Keywords
automatic testing; fault location; integrated circuit testing; logic testing; ATPG performance; fault coverages; invalid states; multiple clock domains; partial set; real circuits; real industrial circuits; sequential learning technique; test generation times; Automatic logic units; Automatic test pattern generation; Circuit testing; Encoding; Graphics; Learning systems; Logic design; Logic testing; Permission; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724547
Link To Document