Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Author

Chelcea, Tiberiu ; Venkataramani, Girish ; Goldstein, Seth C.

Author_Institution

Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA

fYear

2007

fDate

12-14 March 2007

Firstpage

117

Lastpage

128

Abstract

Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous tool flows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.

Keywords

asynchronous circuits; circuit optimisation; logic CAD; area optimization; asynchronous CAD solution; average-case latencies; deep sub-micron technology; dual-rail circuit; heuristic algorithm; relative-timing analysis; Asynchronous circuits; Circuit analysis; Circuit synthesis; Clocks; Computer science; Delay; Design automation; Design optimization; Logic; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems, 2007. ASYNC 2007. 13th IEEE International Symposium on

Conference_Location

Berkeley, CA

ISSN

1522-8681

Print_ISBN

0-7695-2771-X

Type

conf

DOI

10.1109/ASYNC.2007.10

Filename

4137038