A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources

Author

Prevotet, J.C. ; Benkhelifa, A. ; Granado, B. ; Huck, E. ; Miramond, B. ; Verdier, F. ; Chillet, D. ; Pillement, S.

Author_Institution

IETR/INSA, Rennes

fYear

2008

fDate

3-5 Dec. 2008

Firstpage

61

Lastpage

66

Abstract

This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded real time operating systems for reconfigurable System-On-Chip based platforms. Here, we describe the overall methodology and the corresponding design environment. The method is based on abstract and modular SystemC models that allow to explore, simulate, and validate the distribution of OS services on this kind of platform. The experimental results show that our components accurately model the dynamic and deterministic behaviour of RTOS while demonstrating flexible properties.

Keywords

embedded systems; operating systems (computers); reconfigurable architectures; system-on-chip; OveRSoC project; RTOS; abstract SystemC model; design environment; embedded real time operating systems; exploration methodology; hardware reconfigurable resources management; modular SystemC model; reconfigurable system-on-chip based platforms; validation methodology; Circuits; Computer architecture; Context-aware services; Field programmable gate arrays; Hardware; Operating systems; Real time systems; Reconfigurable architectures; Resource management; System-on-a-chip; RTOS; dynamically reconfigurable architectures; high-level modelling;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4244-3748-1

Electronic_ISBN

978-0-7695-3474-9

Type

conf

DOI

10.1109/ReConFig.2008.40

Filename

4731771