An optimization-based error calculation for statistical power estimation of CMOS logic circuits

We present a statistical power estimation method where the estimation time and accuracy can be balanced by assigning smaller errors to the nodes with higher power dissipation and higher errors to the nodes with lower power dissipation. To calculate the error rates for individual nodes, a quadratic programming based problem is formulated which incorporates the distribution data of all individual node switching activities. Also, an iterative statistical power estimation system is presented. Finally, we demonstrate experimental results which show drastic reduction in the number of simulation patterns compared to previous methods.