Title :
Integrating Logic Analyzer Functionality into VHDL Designs
Author :
Knittel, G. ; Mayer, S. ; Rothlaender, C.
Author_Institution :
WSI/GRIS, Univ. of Tubingen, Tubingen
Abstract :
We present a combined hardware and software system for the debugging of FPGA designs. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can insert the analyzer into a user design without manual labor required from the user. All processing is done on the VHDL-level, facilitating vendor-independent, source-level hardware debugging. The system also allows multiple independent FPGA-systems to be debugged in a single framework.
Keywords :
field programmable gate arrays; hardware description languages; logic CAD; logic analysers; FPGA design debugging; VHDL design; logic analyzer functionality; source-level hardware debugging; Debugging; Design automation; Field programmable gate arrays; Hardware; Logic design; Monitoring; Protocols; Reconfigurable logic; Silicon; Software systems; FPGA; On-chip logic analyzer; VHDL;
Conference_Titel :
Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-3748-1
Electronic_ISBN :
978-0-7695-3474-9
DOI :
10.1109/ReConFig.2008.77
