• DocumentCode
    2101082
  • Title

    Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor

  • Author

    Cambre, David M. ; Boemo, Eduardo ; Todorovich, Elías

  • Author_Institution
    Sch. of Comput. Eng., Univ. Autonoma de Madrid, Madrid
  • fYear
    2008
  • fDate
    3-5 Dec. 2008
  • Firstpage
    151
  • Lastpage
    156
  • Abstract
    This paper reports the impact of different Nios II hardware and software options for arithmetic operations on its power and energy consumption. These options are evaluated on the Cyclone II and Stratix II FPGA families using a number of benchmark programs. This analysis is part of a more complete study oriented to characterize the power and energy consumption of an embedded processor like the Alterapsilas Nios II. Results are based on physical measurements and show significant energy savings and higher performance in arithmetic operations when available arithmetic hardware suitable for these operations is included. However when the utilization of resources is taken into account, then setups with less hardware and more software for arithmetic computation can be more efficient.
  • Keywords
    digital arithmetic; field programmable gate arrays; microprocessor chips; power consumption; Cyclone II FPGA family; Nios II embedded processor; Stratix II FPGA family; arithmetic operations; benchmark programs; energy consumption; power consumption; Costs; Cyclones; Design automation; Digital arithmetic; Embedded computing; Embedded software; Embedded system; Energy consumption; Field programmable gate arrays; Hardware; embedded processor; energy evaluation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4244-3748-1
  • Electronic_ISBN
    978-0-7695-3474-9
  • Type

    conf

  • DOI
    10.1109/ReConFig.2008.37
  • Filename
    4731786