FPGA-based measurement and evaluation of power analysis attack resistant asynchronous S-Box

This paper demonstrates a recently proposed low-power side channel attack (SCA) resistant asynchronous S-Box design for the AES crypto-systems. A specified side channel attack standard evaluation FPGA board (SASEBO-GII) is used to implement the design. This board includes two Xilinx FPGAs to perform the cryptographic function and the configuration function separately. This prevents the power trace of the configuration circuit from interfering with the power trace of the cryptographic circuit, so that the measurements of making/resisting power analysis attack can be done fairly. The proposed design is clock free and has flatter power peaks since it is based on a delay-insensitive logic paradigm referred to as null convention logic (NCL). Comparisons between the existing synchronous S-Box design and the proposed asynchronous design are performed in the various aspects; speed, area, total power consumption, and results of differential power analysis (DPA) attack, one of the most powerful cryptanalysis that could extract the secret keys of cryptographic devices. Experimental results shows that the proposed asynchronous S-Box is resistant to DPA attacks and has a lower power consumption than its synchronous counterpart.