Title :
High-speed modular multiplication algorithm for RSA cryptosystem
Author :
Cho, Koon-Shik ; Ryu, Je-Hyuk ; Cho, Jun-dong
Author_Institution :
Autom. Lab, Sung Kyun Kwan Univ., Suwon, South Korea
Abstract :
This paper presents a new radix-4 modular multiplication algorithm based on the sign estimation technique. The sign estimation technique detects the sign of a number represented in the form of a carry-sum pair. It can be implemented with 5-bit carry look-ahead adder. The hardware speed of the cryptosystem is dependent on the performance of modular multiplication of large numbers. Our algorithm requires only n/2+3 clock cycle for n bit modulus in performing modular multiplication. Our algorithm outperforms existing algorithms in terms of required clock cycles by a half. It is efficient for modular exponentiation with large modulus used in the RSA cryptosystem. Also, we use a high-speed adder instead of carry propagation adder for modular multiplication hardware performance in the final stage of the CSA output. We apply the RL (right-and-left) binary method for modular exponentiation because the number of clock cycles required to complete the modular exponentiation takes n cycles. Thus, one 1024-bit RSA operation can be done after n(n/2+3) clock cycles
Keywords :
adders; digital arithmetic; public key cryptography; 1024 bit; RL binary method; RSA cryptosystem; carry-sum pair; high-speed adder; high-speed modular multiplication; modular exponentiation; performance; radix-4 multiplication; right-and-left binary method; sign estimation technique; Algorithm design and analysis; Authentication; Clocks; Communication system security; Data security; Design automation; Hardware; Public key; Public key cryptography; Very large scale integration;
Conference_Titel :
Industrial Electronics Society, 2001. IECON '01. The 27th Annual Conference of the IEEE
Conference_Location :
Denver, CO
Print_ISBN :
0-7803-7108-9
DOI :
10.1109/IECON.2001.976529