A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

Author

Jensen, L.B.W. ; Nielsen, Anders Kjaer ; Alonso, Javier Díaz ; Ros, Eduardo ; Kruger, Norbert

Author_Institution

Maersk Mc-Kinney Moller Inst., Univ. of Southern Denmark, Odense

fYear

2008

fDate

3-5 Dec. 2008

Firstpage

241

Lastpage

246

Abstract

This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC. A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.

Keywords

feature extraction; field programmable gate arrays; parallel architectures; stereo image processing; FPGA; coarse parallel processing architecture; hybrid architecture; multicore PC; multimodal visual feature descriptors; multimodal visual primitives; sparse image descriptors; Cameras; Communication system control; Computer architecture; Computer vision; Concurrent computing; Field programmable gate arrays; Hardware; Machine vision; Multicore processing; Parallel processing; FPGA; biological vision; early cognitive vision;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4244-3748-1

Electronic_ISBN

978-0-7695-3474-9

Type

conf

DOI

10.1109/ReConFig.2008.23

Filename

4731801