Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor

Viterbi decoder implemented with hard-wired logic often requires extra cost and consuming power by using individual logic for various constraint length and decode precisions. Although the redundant hardware which is not used in the given condition can be omitted by replacing the hardwired logic on FPGA, the time for loading configuration data often takes milliseconds and causes too long system stall. In this paper, we implemented the Viterbi algorithms whose constraint length are from 3 to 5 on coarse grained dynamically reconfigurable processor DAPDNA-II and replaced them according to the requirement. A certain threshold of BER is set for a fixed SNR and the Viterbi decoder with multiple constraint lengths is simulated. In the result of evaluation, when at least 4.50 Mbps throughput is ensured even with frequent reconfiguration was performed, the power consumption is reduced by 30% - 80% compared with the case when a constraint length of the best performance is utilized.