DocumentCode
2101570
Title
A soft-core processor array for relational operators
Author
Polig, Raphael ; Giefers, Heiner ; Stechele, Walter
Author_Institution
IBM Research - Zurich, Rueschlikon, Switzerland
fYear
2015
fDate
27-29 July 2015
Firstpage
17
Lastpage
24
Abstract
Despite the performance and power efficiency gains achieved by FPGAs for text analytics queries, analysis shows a low utilization of the custom hardware operator modules. Furthermore the long synthesis times limit the accelerator´s use in enterprise systems to static queries. To overcome these limitations we propose the use of an overlay architecture to share area resources among multiple operators and reduce compilation times. In this paper we present a novel soft-core architecture tailored to efficiently perform relational operations of text analytics queries on multiple virtual streams. It combines the ability to perform efficient streaming based operations while adding the flexibility of an instruction programmable core. It is used as a processing element in an array of cores to execute large query graphs and has access to shared co-processors to perform string-and context-based operations. We evaluate the core architecture in terms of area and performance compared to the custom hardware modules, and show how a minimum number of cores can be calculated to avoid stalling the document processing.
Keywords
Arrays; Field programmable gate arrays; Hardware; Radio frequency; Random access memory; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-specific Systems, Architectures and Processors (ASAP), 2015 IEEE 26th International Conference on
Conference_Location
Toronto, ON, Canada
Type
conf
DOI
10.1109/ASAP.2015.7245699
Filename
7245699
Link To Document