FPGA Implementation of Pseudo Random Number Generators for Monte Carlo Methods in Quantitative Finance

FPGA based implementations of two classes of pseudo random number(PRN) generator, intended for use in Monte Carlo methods for finance, are presented. FPGA implementations potentially offer reduced cost and improved performance compared to general purpose processor (GPP) systems such as PCs or mainframes. The first class of PRN generator, which includes the mersenne twister, uses generalized feedback shift registers (GFSRs). The second class is based on multiplication of fixed precision integers (with overflow). In both cases we compare a high quality generator and a generator with minimal resource usage. Comparisons of FPGA resource usage, data throughput and the quality of the generated series are given with a view to applications in high performance computing (HPC) for computational finance. The two classes of generator are shown to be complementary in their use of FPGA resources.