DocumentCode
2101850
Title
Redundant circuits with latchup protection
Author
Petrovic, V. ; Schoof, G. ; Stamenkovic, Z.
Author_Institution
IHP, Frankfurt (Oder), Germany
fYear
2013
fDate
8-11 Dec. 2013
Firstpage
117
Lastpage
120
Abstract
The paper presents triple and double modular redundant (TMR and DMR) circuits with the latchup protection. Additional logic has been designed to control the latchup protection phase and different power domains. An analytical model for the failure-free probability estimation has been developed too. Test circuits have been implemented and simulated.
Keywords
flip-flops; probability; DMR circuits; TMR circuits; analytical model; double modular redundant circuits; failure-free probability estimation; latchup protection phase; power domains; test circuits; triple modular redundant circuits; Circuit faults; Flip-flops; Redundancy; Switches; Transient analysis; Tunneling magnetoresistance; ASIC design; Fault tolerance; latchup protection; triple and double modular redundancy;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location
Abu Dhabi
Type
conf
DOI
10.1109/ICECS.2013.6815368
Filename
6815368
Link To Document