DocumentCode
2101873
Title
Single event transient mitigation through pulse quenching: Effectiveness at circuit level
Author
Pagliarini, Samuel N. ; de B Naviner, Lirida A. ; Naviner, Jean-Francois
Author_Institution
Inst. MINES-TELECOM, Telecom ParisTech, Paris, France
fYear
2013
fDate
8-11 Dec. 2013
Firstpage
121
Lastpage
124
Abstract
This paper exploits the pulse quenching effect in order to reduce circuit error rates due to single event transients in combinational logic. Although the effect allows for substantial reduction in the sensitive area of a single cell, logical masking at circuit level has to be also considered. Our results show that pulse quenching has a limited effectiveness at circuit level. The results of the proposed approach can be used to drive a reliability-aware design flow.
Keywords
circuit reliability; combinational circuits; logic design; masks; radiation hardening (electronics); circuit error rate reduction; combinational logic; logical masking; pulse quenching effect; reliability-aware design flow; single event transient mitigation; Error analysis; Integrated circuit reliability; Inverters; Layout; Logic gates; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location
Abu Dhabi
Type
conf
DOI
10.1109/ICECS.2013.6815369
Filename
6815369
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