A portable redundancy algorithm for capacitive/resistive SAR A/D converters

Author

Zamprogno, Marco ; Minuti, Alberto ; Girardi, Francesco ; Devecchi, Daniele ; Nicollini, Germano

Author_Institution

ST-Ericsson, Agrate Brianza, Italy

fYear

2013

fDate

8-11 Dec. 2013

Firstpage

141

Lastpage

144

Abstract

An algorithm, which can be used to add redundancy to existing SAR A/D converters for improving their performance, is presented. It needs very small extra analog area and preserves the intrinsic immunity to metastability of a classical SAR algorithm. A 14b Successive Approximation Register (SAR) A/D Converter, equipped with this algorithm, has been designed in a 40nm CMOS process to be embedded in a System-on-Chip (SoC). Maximum DNL/INL of 1.4LSB/3.0LSB and an Effective Number of Bits (ENOB) of 12.0 have been measured.

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit reliability; redundancy; system-on-chip; CMOS process; SAR analog-digital converter redundancy; SoC; capacitive SAR analog-digital converter; portable redundancy algorithm; resistive SAR analog-digital converter; size 40 nm; successive approximation register; system-on-chip; Algorithm design and analysis; CMOS integrated circuits; Capacitors; Oscillators; Redundancy; System-on-chip; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on

Conference_Location

Abu Dhabi

Type

conf

DOI

10.1109/ICECS.2013.6815374

Filename

6815374