FPGA implementation of hierarchical clustering algorithms

In this paper, the design and implementation for computing the Single Linkage (SLINK) and Complete Linkage (CLINK) clustering algorithms on a Field Programmable Gate Array (FPGA) are presented. This research seeks to extend the authors´ previous work, in which novel systolic arrays for implementing the SLINK hierarchical clustering algorithm were presented. As is well known, hierarchical clustering algorithms find applications in many engineering areas, including pattern classification and image processing. However, the execution of these algorithms require considerable CPU time which makes them unsuitable for real-time applications. Our motivation for performing this research is, and has been since our earlier publications, to reduce the CPU time taken for executing the algorithms under discussion. In the present work, our focus is on the implementation of the proposed systolic arrays on a reconfigurable architecture, namely, a Xilinx FPGA. The reconfigurability aspect of the FPGA permits the implementation of both the SLINK and CLINK algorithms on the same FPGA