ADC integral non-linearity testing with low linearity monotonic signals

Author

Vasan, Bharath K. ; Chen, Degang J. ; Geiger, Randall L.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

2011

fDate

10-12 May 2011

Firstpage

1

Lastpage

5

Abstract

Methods to test the Integral Non-Linearity (INL) of Analog-to-Digital Converters (ADCs) using any monotonic signal with low linearity are proposed. Two methods that estimate the INL of the ADC by removing the error due to non-linearity in the stimulus are described. Signals with linearity dramatically lesser than the ADC under test, can be used to accurately estimate the INL of the ADC. Simulation results show that the maximum INL estimation error for testing 14-bit ADCs using 36 dB pure sinusoids and 7-bit linear exponential signals is under 0.6 LSB.

Keywords

analogue-digital conversion; logic testing; 14-bit ADC testing; 7-bit linear exponential signal; ADC integral nonlinearity testing; INL estimation error; analog-to-digital converter; low linearity monotonic signal; word length 14 bit; word length 7 bit; Built-in self-test; Estimation; Histograms; Linearity; Signal generators; Signal resolution; Integral non-linearity (INL); differential non-linearity (DNL); stimulus error identification and removal (SEIR); stimulus error removal (SER);

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference (I2MTC), 2011 IEEE

Conference_Location

Binjiang

ISSN

1091-5281

Print_ISBN

978-1-4244-7933-7

Type

conf

DOI

10.1109/IMTC.2011.5944342

Filename

5944342