DocumentCode
2103355
Title
Analog design procedures for channel lengths down to 20 nm
Author
Sansen, Willy
Author_Institution
K.U. Leuven, Leuven, Belgium
fYear
2013
fDate
8-11 Dec. 2013
Firstpage
337
Lastpage
340
Abstract
A new design procedure is derived for analog design with MOSTs in all three regions of operation i.e. strong and weak inversion and velocity saturation. BSIM6/EKV model parameters are used. Optimum biasing points are derived for single- and two-stage amplifiers. It is shown that for channel lengths around 20 nm, a unique optimum is achieved for the fT × gm/IDS Figure of merit. At such low channel lengths noise and distortion establish severe limitations in dynamic range. They can be mitigated by the use of negative resistors, as used in an increasing number of amplifier and filter configurations. An overview is given of such circuit configurations.
Keywords
MOS analogue integrated circuits; amplifiers; integrated circuit design; BSIM6/EKV model parameters; MOST; amplifier configurations; analog design; biasing points; channel lengths distortion; channel lengths noise; figure of merit; filter configurations; negative resistors; two-stage amplifiers; Abstracts; Capacitance; Electronic mail; Integrated circuit modeling; Noise; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location
Abu Dhabi
Type
conf
DOI
10.1109/ICECS.2013.6815423
Filename
6815423
Link To Document