Electrical analysis to fault isolate defects in 6T memory cells

A simple defect localization scheme for 6 transistor SRAM cells was presented. Parametric measurements for all transistors forming the pull ups and pull downs enable the understanding of the change in feedback behaviour of the memory cell, leading to failure models and defect behaviour. This technique leads to an intuitive and time efficient method to identify failing areas in the memory cell. It underscores the importance of circuit analysis before embarking on physical failure analysis to reduce the area for physical analysis and increase chances of finding the actual defect.