Title :
Overgrown Si/SiGe resonant interband tunnel diodes for integration with CMOS
Author :
Sudirgo, Stephen ; Vega, Reinaldo ; Nandgaonkar, Rohit P. ; Hirschman, Karl D. ; Rommel, Sean L. ; Kurinec, Santosh K. ; Thompson, Philip E. ; Jin, Niu ; Berger, Paul R.
Author_Institution :
Dept. of Microelectron. Eng., Rochester, NY, USA
Abstract :
The incorporation of tunnel diodes with field effect transistors (FET) can improve the speed and power capability in electronic circuitry. This has been realized in III-V materials by demonstrating a low power refresh-free tunneling-SRAM and high performance compact A/D converter. A new thrust to integrate tunnel diodes with the mainstream CMOS technology led to the invention of Si/SiGe resonant interband tunnel diode (RITD) (S.L. Rommel et al., Appl. Phys. Lett., vol. 73, pp. 2191-93, 1998) with the highest reported peak-to-valley current ratio (PVCR) of 6.0 (K. Eberl, J. Crystal Growth, 227-228, pp. 770-76, 2001). The structure consists of a SiGe spacer i-layer sandwiched between two delta-doped planes grown by low-thermal molecular beam epitaxy (LT-MBE) (N. Jin et al., IEEE Trans. Elec. Dev., vol. 50, pp. 1876-1884, 2003). By adjusting the spacer layer thickness, the peak current density (Jp) can be adjusted from 0.1 A/cm2 up to 151 kA/cm2 (N. Jin et al., App. Phys. Lett., 83, pp. 3308-3310, 2003). Recently, monolithic integration of RITD with CMOS has been realized, demonstrating a low-voltage operation of a monostable-bistable logic element (MOBILE) (S.Sudirgo et al., Proc. 2003 Int. Semic. Dev. Res. Symp., pp. 22, 2003). In this study, RITD layers were grown through openings in a 300 nm thick chemical vapor deposition (CVD) SiO2 layer.
Keywords :
CMOS integrated circuits; Ge-Si alloys; current density; doping profiles; elemental semiconductors; integrated circuit measurement; integrated logic circuits; interface structure; molecular beam epitaxial growth; resonant tunnelling diodes; semiconductor growth; semiconductor materials; silicon; 300 nm; A/D converter; CMOS integration; CVD SiO2 layer; III-V materials; LT-MBE; MOBILE low-voltage operation; PVCR; RITD; RITD CMOS monolithic integration; RITD layers; Si-SiGe; SiGe spacer i-layer; delta-doped planes; electronic circuitry; field effect transistors; low power refresh-free tunneling-SRAM; low-thermal molecular beam epitaxy; monostable-bistable logic element; overgrown Si/SiGe resonant interband tunnel diodes; peak current density; peak-to-valley current ratio; power capability; spacer layer thickness; speed capability; tunnel diodes; CMOS technology; Circuits; Current density; FETs; Germanium silicon alloys; III-V semiconductor materials; Light emitting diodes; Molecular beam epitaxial growth; Resonance; Silicon germanium;
Conference_Titel :
Device Research Conference, 2004. 62nd DRC. Conference Digest [Includes 'Late News Papers' volume]
Print_ISBN :
0-7803-8284-6
DOI :
10.1109/DRC.2004.1367807