Contrasting failure characteristics of different levels of Cu dual-damascene metallization

Author

Gan, C.L. ; Wei, F. ; Thompson, C.V. ; Pey, K.L. ; Choi, W.K. ; Hau-Riege, S.P. ; Yu, B.

Author_Institution

Adv. Mater. for Micro- & Nano-Syst. Programme, Singapore-MIT Alliance, Singapore, Singapore

fYear

2002

fDate

2002

Firstpage

124

Lastpage

128

Abstract

Currently, several kilometers of interconnects are used to construct a state-of-the-art Si-based integrated circuit, which has up to 8 levels of metallization. The failure mechanisms and reliability of the different layers of metallization are assumed to be the same in circuit-level reliability analysis. Although this may be true in Al interconnects, it may not be so for Cu dual-damascene lines. In this paper, we report on differences in the failure mechanisms between the first (M1) and second (M2) levels of Cu metallization, and how it affects the overall circuit reliability for Cu metallization.

Keywords

copper; electromigration; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; voids (solid); Al interconnects; Cu; Cu dual-damascene lines; Cu dual-damascene metallization; Si-based integrated circuits; circuit-level reliability analysis; contrasting level failure characteristics; copper interconnects; electromigration; failure mechanisms; first/second metallization levels; specific layer reliability; void formation; Bonding; Copper; Dielectrics; Electromigration; Failure analysis; Integrated circuit interconnections; Integrated circuit reliability; Metallization; Packaging; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the

Print_ISBN

0-7803-7416-9

Type

conf

DOI

10.1109/IPFA.2002.1025630

Filename

1025630