Title :
A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier
Author :
Donida, Achille ; Malcovati, Piero ; Cellier, Remy ; Nagari, Angelo ; Baschirotto, A.
Author_Institution :
Dept. of Electr., Comput., & Biomed. Eng., Univ. of Pavia, Pavia, Italy
Abstract :
This paper presents a continuous-time 3rd order ΣΔ modulator implemented in 40-nm CMOS technology for closing the feedback loop of a digital class-D audio amplifier. The proposed ΣΔ A/D converter consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB DR and 72-dB peak SNDR. The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees 3rd order anti-aliasing filtering.
Keywords :
CMOS integrated circuits; amplifiers; sigma-delta modulation; CMOS integrated circuit; active RC implementation; continuous-time sigma-delta ADC; digital closed loop class D amplifier; power 1.7 mW; size 40 nm; third order antialiasing filtering; voltage 1.1 V; CMOS integrated circuits; CMOS technology; Power demand; Pulse width modulation; Topology;
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location :
Abu Dhabi
DOI :
10.1109/ICECS.2013.6815448
