DocumentCode
2104034
Title
Multiple techniques approach failure analysis for a blocked p+ implant induced leakage in an ESD protection diode
Author
Wong, V.K. ; Low, P.F. ; Lock, C.H. ; Siek, K.H.
Author_Institution
Intel Technol. Sdn. Bhd., Penang, Malaysia
fYear
2002
fDate
2002
Firstpage
183
Lastpage
186
Abstract
In this paper, we present the multiple techniques analysis of a blocked p+ implant in a p+/N-well diode which forms the ESD protection of a pin. We will describe the leakage model and various observations that are made by advanced failure analysis tools. Since the pn junction forms one of the fundamental devices in realizing the MOSFET, the understanding of the characteristics of the malformed diode is crucial for predicting the effect of partially blocked source/drain implants for future failure analysis.
Keywords
electrostatic discharge; failure analysis; ion implantation; leakage currents; protection; semiconductor diodes; ESD protection diode; MOSFET; blocked p+ implant induced leakage; failure analysis; leakage model; p-n junction; Assembly; Circuits; Diodes; Electrostatic discharge; Failure analysis; Implants; Optical microscopy; Pins; Protection; Strips;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the
Print_ISBN
0-7803-7416-9
Type
conf
DOI
10.1109/IPFA.2002.1025649
Filename
1025649
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