Title :
A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 Mb embedded DRAM and a 5 GOPS adaptive post filter
Author :
Arakida, H. ; Takahashi, M. ; Tsuboi, Y. ; Nishikawa, T. ; Yamamoto, H. ; Fujiyoshi, T. ; Kitasho, Y. ; Ueda, Y. ; Watanabe, M. ; Fujita, T. ; Terazawa, T. ; Ohmori, K. ; Koana, M. ; Nakamura, H. ; Watanabe, E. ; Ando, H. ; Aikawa, T. ; Furuyama, T.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A single-chip MPEG-4 audiovisual LSI in a 0.13 /spl mu/m 5M CMOS technology with 16 Mb embedded DRAM is presented. Four 16 b RISC processors and dedicated hardware accelerators including a 5 GOPS post filtering engine are integrated on the IC. The chip consumes 160 mW at 125 MHz and uses 80 nA in the standby mode. This LSI handles MPEG-4 CIF video encoding at 15 frames/s and audio encoding simultaneously.
Keywords :
CMOS digital integrated circuits; DRAM chips; adaptive filters; audio-visual systems; digital signal processing chips; multimedia communication; reduced instruction set computing; speech codecs; video codecs; 125 MHz; 16 Mb embedded DRAM; 16 Mbit; 16 bit; 160 mW; 5 GOPS adaptive post filter; 5M CMOS technology; 80 nA; MPEG-4 CIF video encoding; MPEG-4 audiovisual LSI; MPEG-4 video codec; RISC processors; audio encoding; dedicated hardware accelerators; post filtering engine; power consumption; speech codec; standby mode; Adaptive filters; CMOS technology; Encoding; Engines; Filtering; Hardware; Large scale integration; MPEG 4 Standard; Random access memory; Reduced instruction set computing;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234199
