An FPGA implementation of NIST 256 prime field ECC processor

In this paper, we propose a new Application Specific Instruction-set (ASIP) ECC processor based on Redundant Signed Digit representation with a novel Iterative-Recursive Karatsuba multiplier. The results of Vertix-5 FPGA implementation with full CLB based design is presented in this paper. The processor performs point multiplication for NIST recommended curve P256 and is based on an extended NIST reduction scheme. Our processor performs single point multiplication where points are represented in affine coordinates within 6.67 ms and runs at maximum frequency of 66.3 MHz. The design of our processor is entirely based on CLB blocks as opposed to other FPGA implementations.