Title :
A 1.5V 1mA 80dB passive /spl Sigma//spl Delta/ ADC in 0.13/spl mu/m digital CMOS process
Author :
Feng Chen ; Ramaswamy, S. ; Bakkaloglu, B.
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A passive switched-capacitor /spl Sigma//spl Delta/ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13/spl mu/m digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.
Keywords :
CMOS integrated circuits; cellular radio; high-speed integrated circuits; low-power electronics; sigma-delta modulation; switched current circuits; transceivers; 0.13 micron; 1 mA; 1.5 V; 100 kHz; 104 MHz; SFDR; SNDR; digital CMOS process; dynamic range; high-speed low-voltage architecture; passive switched-capacitor sigma-delta ADC; zero-IF GSM transceiver; Attenuation; Baseband; CMOS process; Feedback; Filtering; Low pass filters; Quantization; Sampling methods; Signal to noise ratio; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234204
