Title :
A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization
Author :
Bong-Joon Lee ; Moon-Sang Hwang ; Sang-Hyun Lee ; Deog-Kyoon Jeong
Author_Institution :
Seoul Nat. Univ., South Korea
Abstract :
A 2.5 to 10 Gb/s CMOS transceiver in 0.18 /spl mu/m CMOS dissipates 540 mW from a 1.8 V supply with a BER better than 10/sup -12/. CDR loop characteristics are stabilized across various jitter environments with small hardware overhead using an alternating edge sampling phase detector.
Keywords :
CMOS digital integrated circuits; circuit stability; jitter; low-power electronics; phase detectors; signal sampling; synchronisation; transceivers; 0.18 micron; 1.8 V; 2.5 to 10 Gbit/s; 540 mW; BER; CDR loop characteristics; CMOS transceiver; alternating edge sampling phase detection; clock and data recovery; jitter environments; loop characteristic stabilization; oversampling technique; power dissipation; up/down decisions; Charge pumps; Clocks; Frequency locked loops; Image edge detection; Image sampling; Jitter; Phase detection; Sampling methods; Silicon; Transceivers;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234214
