Title :
Correlation between interface traps and gate leakage current in ultrathin silicon dioxides
Author :
Wei-Yip Loh ; Byung-Jin Cho
Abstract :
In ultra-thin (20 Å) gate oxide, it is observed that gate leakage current increases in discrete steps similar to quasi-breakdown in thicker oxide. A direct correlation is observed between this gate leakage and interface traps when stressed under both positive and negative gate polarity. Using different sample area, it is observed that this gate leakage current is highly localized but has a weak area dependency.
Keywords :
CMOS integrated circuits; MOSFET; dielectric thin films; interface states; leakage currents; semiconductor-insulator boundaries; silicon compounds; 20 A; CMOS technology; SiO2; gate leakage current; interface traps; negative gate polarity; p-MOSFETs; positive gate polarity; ultra-thin gate oxide; Bipolar transistors; CMOS technology; Degradation; Dielectric devices; Electric breakdown; Energy dissipation; Gate leakage; Leakage current; Silicon compounds; Tunneling;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the
Print_ISBN :
0-7803-7416-9
DOI :
10.1109/IPFA.2002.1025672
