A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

Author

Zhiwei Xu ; Hyunchol Shin ; Jongsun Kim ; Chang, M.F. ; Chien, C.

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

82

Abstract

A 2.7 Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18 /spl mu/m CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8 ns. The chip-set dissipates 74 mW and occupies 0.3 mm/sup 2/ per I/O pair.

Keywords

CMOS integrated circuits; code division multiple access; integrated circuit interconnections; mixed analogue-digital integrated circuits; reconfigurable architectures; synchronisation; transceivers; voltage-controlled oscillators; 0.18 /spl mu/m CMOS technology; 0.18 micron; 0.8 ns; 2.7 Gbit/s; 74 mW; Alexander-type multi-level data recovery circuit; CDMA-interconnect transceiver chip set; LC VCO; multi-level signal data recovery; multiple I/O communication; multiple I/O signal routes; power dissipation; real-time system reconfigurability; reconfigurable VLSI systems; symbol period; CMOS technology; Circuits; Clocks; Modulation coding; Multiaccess communication; Synchronization; Throughput; Transceivers; Very large scale integration; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234217

Filename

1234217