A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technology

Author

Kawaguchi, Hitoshi ; Kanda, K. ; Nose, Keisuke ; Hattori, Saki ; Dwi, D. ; Antono, D. ; Yamada, Daichi ; Miyazaki, Toshimasa ; Inagaki, K. ; Hiramoto, Toshiro ; Sakurai, Takayasu

Author_Institution

University of Tokyo, Japan

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

106

Abstract

A 0.5V, 400MHz, 3.5mW, 16b RISC processor with a 0.25/spl mu/m, dual V/sub T/, fully-depleted SOI technology is presented. Zero V/sub T/ is used in logic for high speed while memories and register files adopt a higher V/sub 00/ and V/sub T/ to suppress leakage. Experimental results show that V/sub 00/-hopping is effective in leakage dominant environments.

Keywords

high-speed integrated circuits; leakage currents; microprocessor chips; reduced instruction set computing; silicon-on-insulator; 0.25 micron; 0.5 V; 16 bit; 3.5 mW; 400 MHz; RISC processor; V/sub 00/-hopping processor; dual-V/sub T/ fully-depleted SOI technology; high-speed operation; leakage suppression; zero-V/sub TH/ FD-SOI technology; Decoding; Energy consumption; Logic; MOS devices; Nose; Random access memory; Registers; Silicon on insulator technology; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234227

Filename

1234227