Title :
A 9/spl mu/W 50MHz 32b adder using a self-adjusted forward body bias in SoCs
Author :
Ishibashi, K. ; Yamashita, T. ; Arima, Y. ; Minematsu, I. ; Fujimoto, T.
Author_Institution :
STARC, Yokohama, Japan
Abstract :
This 32b adder in a 0.13/spl mu/m CMOS process consumes 9/spl mu/W at 50MHz and 0.3V and operates at 500MHz at 0.6V. Forward body biases are self-adjusted to minimize the threshold voltage and reduce PVT dependence. The power of the SoC can be reduced to 1/4 that of standard CMOS by gating the forward body bias in the IP blocks.
Keywords :
CMOS logic circuits; adders; low-power electronics; system-on-chip; 0.13 micron; 0.3 V; 0.6 V; 32 bit; 50 MHz; 500 MHz; 9 muW; CMOS process; IP block; PVT dependence; adder; low-power system-on-chip; self-adjusted forward body bias; threshold voltage; Adders; Circuit testing; Delay; Diodes; Frequency; Low voltage; Semiconductor device measurement; System-on-a-chip; Temperature dependence; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234232
