Title :
A 1.5 V 14 b 100 MS/s self-calibrated DAC
Author :
Yonghua Cong ; Geiger, R.L.
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
A calibrated 14 b current-steering DAC is fabricated in a 0.13 /spl mu/m digital CMOS process. The DAC achieves 14 b static linearity with a single 1.5 V supply, and the core occupies 0.1 mm/sup 2/. Dynamic linearity is improved through reduction of parasitic effects. At 100 MS/s, the SFDR is 82 dB and 62 dB at signals of 0.9 MHz and 42.5 MHz, respectively. Power consumption is 16.7 mW.
Keywords :
CMOS integrated circuits; calibration; digital-analogue conversion; 0.9 to 42.5 MHz; 1.5 V; 14 bit; 16.7 mW; current-steering DAC; digital CMOS process; dynamic linearity; parasitic effects reduction; self-calibrated DAC; Application software; Calibration; Computer errors; Frequency domain analysis; Linearity; Parasitic capacitance; Routing; Telecommunication computing; Telecommunication switching; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234234
