Title :
A single-chip 802.11a MAC/PHY with a 32 b RISC processor
Author :
Fujisawa, T. ; Hasegawa, J. ; Tsuchie, K. ; Shiozawa, T. ; Fujita, T. ; Seki-Fukuda, K. ; Higashi, T. ; Bandar, R. ; Yoshida, N. ; Shinohara, K. ; Watanabe, T. ; Hatanoz, H. ; Noguchiz, K. ; Saito, T. ; Unekawa, Y. ; Aikawa, T.
Author_Institution :
Toshiba Corp. Semicond., Kawasaki, Japan
Abstract :
An 802.11a compliant MAC/PHY processing chip has been successfully fabricated in 0.18 /spl mu/m CMOS. Thirty million transistors are integrated on a 10.91 /spl times/ 10.91 mm/sup 2/ die in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32 b RISC processor and hardware acceleration logic. The PHY supports a complete set of data rates up to 54 Mb/s.
Keywords :
CMOS digital integrated circuits; microprocessor chips; reduced instruction set computing; 0.18 micron; 32 bit; 54 Mbit/s; CMOS IC; PFBGA; RISC processor; compliant MAC/PHY processing chip; hardware acceleration logic; single-chip 802.11a MAC/PHY; Broadcasting; Energy management; Frequency estimation; Gain control; Hardware; Microprogramming; Physical layer; Reduced instruction set computing; Traffic control; Unicast;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234241
