DocumentCode
2105234
Title
A 13.3Mb/s 0.35/spl mu/m CMOS analog turbo decoder IC with a configurable interleaver
Author
Gaudet, V.C. ; Gulak, P.G.
Author_Institution
Toronto Univ., Ont., Canada
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
148
Abstract
A 0.35/spl mu/m CMOS analog decoder for a 4-state, rate 1/3, block length 16 turbo code operates at 13.3Mb/s and latency of 1.2/spl mu/s and consumes 13.9nJ per decoded bit with a 3.3V supply. The 1.42mm/sup 2/ core IC implements two logarithmic domain MAP decoders and a fully programmable analog interleaver that is configured at power-up.
Keywords
CMOS analogue integrated circuits; analogue processing circuits; interleaved codes; maximum likelihood decoding; 0.35 micron; 1.2 mus; 13.3 Mbit/s; 13.9 nJ; 3.3 V; CMOS; analog turbo decoder IC; block length; configurable interleaver; fully programmable analog interleaver; latency; logarithmic domain MAP decoders; Analog integrated circuits; CMOS analog integrated circuits; CMOS integrated circuits; Capacitors; Digital video broadcasting; Energy consumption; Feedback loop; Iterative decoding; Transconductors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234243
Filename
1234243
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