Title :
A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC
Author :
Bougard, B. ; Giulietti, A. ; Derudder, V. ; Weijers, J.-W. ; Dupont, S. ; Hollevoet, L. ; Catthoor, F. ; Van der Perre, L. ; De Man, H. ; Lauwereins, R.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup 2/. Energy-optimized architecture reduces the energy per bit to 8.7nJ and is almost constant over the throughput range.
Keywords :
codecs; concatenated codes; convolutional codes; turbo codes; 0.18 micron; 6 to 75.6 Mbit/s; 8.25 dB; 8.7 nJ; integrated circuit; parallel concatenated convolutional turbo CODEC; Clocks; Codecs; Communication standards; Concatenated codes; Convolutional codes; Energy consumption; Forward error correction; Interleaved codes; Iterative decoding; Throughput;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234245
