DocumentCode
2105468
Title
A wire-delay scalable microprocessor architecture for high performance systems
Author
Keckler, S.W. ; Burger, D. ; Moore, C.R. ; Nagarajan, R. ; Sankaralingam, K. ; Agarwal, V. ; Hrishikesh, M.S. ; Ranganathan, N. ; Shivakumar, P.
Author_Institution
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
168
Abstract
This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15/spl times/ more instructions per clock than conventional superscalar architectures.
Keywords
computer architecture; delays; microprocessor chips; chained ALUs; dependent instructions; high performance systems; instructions per clock; on-chip wire delays; physical distance; wire-delay scalable microprocessor architecture; Clocks; Computer architecture; Concurrent computing; Delay; Energy consumption; Microprocessors; Pipelines; Pulse inverters; Registers; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234252
Filename
1234252
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