Title :
1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme
Author :
Kanda, K. ; Antono, D.D. ; Ishida, K. ; Kawaguchi, H. ; Kuroda, T. ; Sakurai, T.
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Japan
Abstract :
A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm/sup 2/. The interface utilizes capacitively coupled contactless minipads, return-to-half-V/sub 00/ signaling and sense amplifying F/F. The measured test chip fabricated in 0.35/spl mu/m CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
Keywords :
CMOS integrated circuits; coupled circuits; high-speed integrated circuits; integrated circuit interconnections; low-power electronics; 0.35 micron; CMOS; capacitively coupled contactless minipads; high-speed chip-to-chip interface scheme; low-power IC; return-to-half-V/sub 00/ signaling; sense amplifying F/F; wireless superconnect; Bandwidth; Capacitance; Capacitors; Coupling circuits; Driver circuits; Electrostatic discharge; Personal communication networks; Protection; Transmitters; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234260
