DocumentCode :
2105684
Title :
Planarized InP/InGaAs heterojunction bipolar transistors with fMAX > 500 GHz
Author :
Sawdai, D. ; Chang, P.C. ; Gambin, V. ; Zeng, X. ; Yamamoto, J. ; Loi, K. ; Leslie, G. ; Barsky, M. ; Gutierrez-Aitken, A. ; Oki, A.
Author_Institution :
Northrop Grumman Space Technol., Redondo Beach, CA, USA
fYear :
2004
fDate :
21-23 June 2004
Firstpage :
14
Abstract :
To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (WE) and the base-collector junction capacitance (CBC), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both WE and CBC using production I-line lithography, resulting in emitters as small as 0.14 μm, unity gain cutoff frequency (fT) up to 290 GHz, and maximum oscillation frequency (fMAX) greater than 500 GHz.
Keywords :
heterojunction bipolar transistors; photolithography; planarisation; submillimetre wave transistors; 0.14 micron; 290 GHz; 500 GHz; I-line lithography; InP-InGaAs; aggressive scaling; base-collector junction capacitance; dielectric planarization process; emitter size; emitter width minimization; heterojunction bipolar transistors; lateral scaling; maximum oscillation frequency; planarized HBT; transit time minimization; unity gain cutoff frequency; vertical scaling; Capacitance; Circuits; Cutoff frequency; Dielectrics; Heterojunction bipolar transistors; High-speed electronics; Indium gallium arsenide; Indium phosphide; Planarization; Production;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference, 2004. 62nd DRC. Conference Digest [Includes 'Late News Papers' volume]
ISSN :
1548-3770
Print_ISBN :
0-7803-8284-6
Type :
conf
DOI :
10.1109/DRC.2004.1367903
Filename :
1367903
Link To Document :
بازگشت