DocumentCode
2106130
Title
Addition and multiplication scheme for energy-efficient DSP component
Author
Wang, Hongfan ; Margala, Martin
Author_Institution
TRLabs Edmonton, Edmonton, Alta., Canada
Volume
2
fYear
2000
fDate
2000
Firstpage
636
Abstract
The design of various fixed-number adders and multipliers is reviewed. This includes different addition and multiplication schemes, circuit design styles, also mentioned are common characterization criterions and test strategies. Finally, the design of a reconfigurable, high throughput yet power efficient multiplication component is proposed, taking the form of a soft macro (core)
Keywords
VLSI; adders; digital arithmetic; digital signal processing chips; integrated circuit design; macros; multiplying circuits; VLSI circuit design; addition; circuit design; energy-efficient DSP component; fixed-number adders; fixed-number multipliers; high throughput multiplication component; multiplication; power efficient multiplication component; reconfigurable efficient multiplication component; soft macro; test strategies; Adders; Arithmetic; Circuit synthesis; Circuit testing; Digital signal processing; Energy consumption; Energy efficiency; Silicon; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 2000 Canadian Conference on
Conference_Location
Halifax, NS
ISSN
0840-7789
Print_ISBN
0-7803-5957-7
Type
conf
DOI
10.1109/CCECE.2000.849543
Filename
849543
Link To Document