DocumentCode :
2106260
Title :
A 4th order band pass sigma-delta modulator using carry-save for digital IF quadrature modulator
Author :
Ruimin Huang ; Zhen Yan ; Chaodong Ling ; Lotze, N. ; Manoli, Yiannos
Author_Institution :
Coll. of Inf. Sci. & Eng, Huaqiao Univ., Xiamen, China
fYear :
2012
fDate :
9-11 Nov. 2012
Firstpage :
1257
Lastpage :
1261
Abstract :
This paper presents a digital intermediate frequency (IF) quadrature modulator realized by a single-bit band pass sigma-delta DAC, in which a pair of single-bit-low-pass sigma-delta digital modulators is used to share the computation for doubling the speed. Fractional-delay interpolation filters are added before the sigma-delta modulators to adjust the interleaved timing relationship between the IQ paths. Carry-save algorithm is used to increase the computation speed in both sigma-delta modulators and interpolation filters, which leads to a speed improvement with little area overhead. The simulation results show that the proposed design can realize a single bit 4th order band pass sigma-delta DAC whose sampling frequency reach hundreds Mhz, and whose SFDR is up to 65 dB.
Keywords :
band-pass filters; digital-analogue conversion; frequency modulation; interpolation; modulators; sigma-delta modulation; 4th order band pass sigma-delta modulator; IQ paths; SFDR; carry-save algorithm; computation speed; digital IF quadrature modulator; digital intermediate frequency quadrature modulator; fractional-delay interpolation filters; interpolation filters; single-bit band pass sigma-delta DAC; single-bit-low-pass sigma-delta digital modulators; 2′ complement; Carry Save; DSP; Modulo Arithmetic; Sigma Delta Modulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication Technology (ICCT), 2012 IEEE 14th International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4673-2100-6
Type :
conf
DOI :
10.1109/ICCT.2012.6511390
Filename :
6511390
Link To Document :
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