A fully integrated 43.2 Gb/s clock and data recovery and 1:4 DEMUX IC in InP HBT technology

Author

Yen, J. ; Case, M.G. ; Nielsen, S. ; Rogers, J.E. ; Srivastava, N.K. ; Thiagarajah, R.

Author_Institution

Inphi, Westlake Village, CA, USA

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

240

Abstract

A 43.2 Gb/s CDR/DMUX IC implemented in InP HBT technology is fully integrated, requiring only a single external capacitor for complete functionality. Sensitivity is 27 mV/sub p-p/ differential with a BER of 10/sup -12/. The IC exceeds extrapolated SONET jitter tolerance specifications, operates with a 3.3 V power supply, and dissipates 3.3 W in 10.2 mm/sup 2/.

Keywords

III-V semiconductors; SONET; bipolar integrated circuits; demultiplexing equipment; digital communication; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; jitter; mixed analogue-digital integrated circuits; optical communication equipment; optical fibre communication; synchronisation; 3.3 V; 3.3 W; 43.2 Gbit/s; BER; CDR/DMUX IC; InP; InP HBT technology; SONET jitter tolerance specifications; clock and data recovery; Clocks; Detectors; Frequency conversion; Heterojunction bipolar transistors; Indium phosphide; Integrated circuit interconnections; Latches; Phase detection; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234284

Filename

1234284