Author :
Kowaleski, J.A., Jr. ; Truex, T. ; Dever, D. ; Ament, D. ; Anderson, W. ; Bair, L. ; Bakke, S. ; Bertucci, D. ; Castelino, R. ; Clay, D. ; Clouser, J. ; DiPace, A. ; Germini, V. ; Hokinson, R. ; Houghton, C. ; Kolk, H. ; Miller, B. ; Moyer, G. ; Mueller,
Author_Institution :
Hewlett Packard, Shrewsbury, MA, USA
Abstract :
Conversion of a 150 million transistor microprocessor from a 0.18 /spl mu/m bulk process to a 0.13 /spl mu/m SOI process is described. Shorter channels and SOI characteristics cause leakage that must be managed. System requirements drive duplication of signal characteristics and integrity for all I/O. Adaptation of the Si to a 200 /spl mu/m bump structure that is 50 /spl mu/m smaller than the previous generation is shown.
Keywords :
CMOS digital integrated circuits; VLSI; integrated circuit layout; leakage currents; microprocessor chips; silicon-on-insulator; 0.13 micron; 0.18 micron; 200 micron; Alpha microprocessor; Rambus open-drain driver; Si; bulk-to-SOI conversion; bump grid array; feature size reduction; floorplan; interprocessor bus interface; partially depleted SOI process; Capacitance; Central Processing Unit; Circuits; Degradation; Microprocessors; Noise level; Packaging; Sun; Testing; Voltage;
