Title :
A 1.5 GHz third generation Itanium/spl reg/ processor
Author :
Stinson, J. ; Rusu, S.
Author_Institution :
Intel, Santa Clara, CA, USA
Abstract :
A third-generation 1.5 GHz Itanium/spl reg/ processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6 MB, 24-way set associative L3 cache. The 374 mm/sup 2/ die contains 410M transistors and is implemented in a dual-V/sub T/ 0.13 /spl mu/m technology having 6-level Cu interconnects with FSG dielectric and dissipates 130 W.
Keywords :
CMOS digital integrated circuits; VLSI; cache storage; copper; high-speed integrated circuits; integrated circuit interconnections; microprocessor chips; parallel architectures; 0.13 micron; 1.5 GHz; 130 W; 24-way set associative L3 cache; 6-level Cu interconnects; Cu; FSG dielectric; dual-V/sub T/ technology; explicitly parallel instruction computing architecture; third generation Itanium processor; Clocks; Computer aided instruction; Computer architecture; Concurrent computing; Copper; Delay; Dielectrics; Integrated circuit interconnections; Power dissipation; Registers;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234289
