Title :
A 600 MHz NT3 network processor
Author :
McMahan, S. ; Erickson, B. ; McMahon, S. ; Huxel, J. ; Husrieh, A. ; Zhimin Wen ; Steiss, D.
Author_Institution :
NPU Eng., Cisco Syst., Richardson, TX, USA
Abstract :
A 97M transistor custom-designed network processor integrating 16 VLIW CPUs implements the Cisco Toaster instruction set at 600 MHz in a 0.18 /spl mu/m process. The chip area is 349 mm/sup 2/ and consumes 20 W at 500 MHz. The frequency is 2.5/spl times/ that of an ASIC Toaster implementation in a similar process.
Keywords :
CMOS digital integrated circuits; high-speed integrated circuits; instruction sets; microprocessor chips; network computers; parallel architectures; 0.18 micron; 20 W; 600 MHz; Cisco Toaster instruction set; NT3 network processor; VLIW CPUs; custom-designed network processor; Bandwidth; Clocks; Frequency; Libraries; Logic; Phase locked loops; Phased arrays; Random access memory; Testing; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234291
