Title :
A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS
Author :
Hoskote, Y. ; Erraguntla, V. ; Finan, D. ; Howard, J. ; Klowden, D. ; Narendra, S. ; Ruhl, G. ; Tschanz, J. ; Vangal, S. ; Veeramachaneni, V. ; Wilson, H. ; Jianping Xu ; Borkar, N.
Author_Institution :
Microprocessor Res. Labs, Intel, Hillsboro, OR, USA
Abstract :
This prototype offloads TCP input processing on minimum packet sizes at wire speed for 10Gb/s Ethernet. The design employs a 10GHz core with a specialized instruction set and includes hardware support for dynamically reordering packets. In a 90nm dual-V/sub T/ CMOS process, the 8mm/sup 2/ chip has 260K transistors. Simulation predicts a power dissipation of 1.9W at 1.2V and 10GHz.
Keywords :
CMOS digital integrated circuits; local area networks; microprocessor chips; transport protocols; 1.2 V; 1.9 W; 10 GHz; 10 Gbit/s; 90 nm; Ethernet; TCP offload accelerator; dual-V/sub T/ CMOS process; dynamic packet reordering; instruction set; microprocessor chip; CADCAM; Computer aided manufacturing; Ethernet networks; Frequency; Hardware; Out of order; Protocols; Prototypes; Read only memory; Wire;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234292
