• DocumentCode
    2106759
  • Title

    Fixed-depth interconnection networks

  • Author

    Hegde, R. ; El-Amawy, A.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
  • fYear
    1989
  • fDate
    26-28 Mar 1989
  • Firstpage
    226
  • Lastpage
    230
  • Abstract
    Interconnection networks that have D stages with K ×K switches, where D and K are powers of 2, are analyzed. The number of stages is held fixed irrespective of the number of processing elements in the system. These networks lie somewhere in the range between single-stage and multistage networks. The performance of these networks in terms of delay time for one-to-one connections, hardware complexity, and permuting abilities are considered. Routing tag schemes for routing data items through the network are presented. The D-stage network is compared with two well-known multistage networks in terms of the above-mentioned performance parameters
  • Keywords
    multiprocessor interconnection networks; network topology; parallel processing; computer networks; data routeing; hardware complexity; interconnection networks; multistage networks; parallel processing; Communication switching; Concurrent computing; Delay effects; Feedback; Hardware; Multiprocessor interconnection networks; Parallel processing; Performance analysis; Routing; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System Theory, 1989. Proceedings., Twenty-First Southeastern Symposium on
  • Conference_Location
    Tallahassee, FL
  • ISSN
    0094-2898
  • Print_ISBN
    0-8186-1933-3
  • Type

    conf

  • DOI
    10.1109/SSST.1989.72466
  • Filename
    72466