DocumentCode
2106950
Title
A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write
Author
Taito, Y. ; Tanizaki, T. ; Kinoshita, M. ; Igaue, F. ; Fujino, T. ; Arimoto, K.
Author_Institution
Mitsubishi Electr. Corp., Hyogo, Japan
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
306
Abstract
A high density memory (HDRAM) for SoC with SRAM interface is described. This macro achieves no-wait fast random-cycle operation owing to a sense-synchronized read/write scheme. A 4Mb test device is fabricated in a 0.15/spl mu/m process and achieves 143MHz operation. Its size and standby power are 4.59mm/sup 2/ and 92mW, which are 30% and 4.8%, respectively, of an embedded SRAM macro fabricated identically.
Keywords
DRAM chips; system-on-chip; timing; 0.15 micron; 143 MHz; 4 Mbit; 92 mW; HDRAM; SRAM interface; SoC; high density memory; no-wait fast random-cycle operation; sense-synchronized-read/write; size; standby power; Circuit simulation; Delay effects; Energy consumption; Flip-flops; Logic circuits; MOSFETs; Random access memory; Temperature sensors; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234310
Filename
1234310
Link To Document