DocumentCode
2106960
Title
A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface
Author
Pilo, H. ; Anand, D. ; Barth, J. ; Burns, S. ; Corson, P. ; Covino, J. ; Houghton, R. ; Lamphier, S.
Author_Institution
IBM Microeletronics, Essex Junction, VT, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
308
Abstract
A 144 Mb DRAM operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121 mm/sup 2/ die is fabricated in a 0.13 /spl mu/m logic-based process. The cycle-time is achieved using an early-write sensing technique. Dynamic-precharge decoding and improved data-formatting circuits produce latencies of 5.0 ns.
Keywords
CMOS memory circuits; DRAM chips; SRAM chips; timing; 0.13 micron; 0.13 mm logic-based process; 144 Mb DRAM; 144 Mbit; 5 ns; 5.6 ns; 5.6 ns random cycle; DDR3-SRAM interface; data rates; data-eye window; data-formatting circuits; dynamic-precharge decoding; early-write sensing technique; latencies; timing diagrams; Bandwidth; Clocks; Copper; Delay; FETs; Integrated circuit interconnections; Microelectronics; Protocols; Random access memory; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234311
Filename
1234311
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