Title :
A 2 GS/s 6 b ADC in 0.18 /spl mu/m CMOS
Author :
Xicheng Jiang ; Zhengyu Wang ; Chang, M.F.
Author_Institution :
California Univ., Los Angeles, CA, USA
Abstract :
A 2 GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18 /spl mu/m CMOS. Three cross-connected and pre-distorted reference voltages improve the averaging performance. Circuit techniques enabling an SNDR of 30 dB at Nyquist input frequency and a FOM of 3.5 pJ per conversion step are discussed, and experimental results validating the simulated performance metrics are presented.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; reference circuits; 0.18 /spl mu/m CMOS; 0.18 micron; 2 GS/s 6-bit ADC; 6 bit; FOM; Nyquist input frequency; SNDR; averaging performance; circuit techniques; cross-connected pre-distorted reference voltages; figure-of-merit; simulated performance metrics; time-interleaving; Bandwidth; Circuits; Clocks; Differential amplifiers; Energy consumption; Frequency; Latches; Preamplifiers; Resistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234317
