A 10 b 150 MS/s 123 mW 0.18 /spl mu/m CMOS pipelined ADC

Author

Sang-Min Yoo ; Jong-Bum Park ; Hee-Suk Yang ; Hyuen-Hee Bae ; Kyoung-Ho Moon ; Ho-Jin Park ; Seung-Hoon Lee ; Jae-Hwui Kim

Author_Institution

Samsung Electron., Yongin, South Korea

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

326

Abstract

A 10 b 150 MHz multi-bit-per-stage single-channel CMOS pipelined ADC, incorporating temperature- and supply-insensitive CMOS references and improved gate-bootstrapping techniques for a wideband SHA, achieves a SNDR of 52 dB and SFDR of 65 dB at 150 MS/s. The ADC, fabricated in 0.18 /spl mu/m CMOS, occupies an active die area of 2.2 mm/sup 2/ and consumes 123 mW at 1.8 V.

Keywords

CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; low-power electronics; pipeline processing; reference circuits; signal sampling; 0.18 /spl mu/m CMOS; 0.18 micron; 1.8 V; 10 bit; 123 mW; 150 MHz; CMOS pipelined ADC; SFDR; SNDR; active die area; gate-bootstrapping techniques; multi-bit-per-stage single-channel CMOS pipelined ADC; power consumption; supply-insensitive CMOS references; temperature-insensitive CMOS references; wideband SHA; Breakdown voltage; Capacitors; Clocks; Current supplies; MOS devices; Power supplies; Sampling methods; Switches; Switching circuits; Wireless networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234319

Filename

1234319